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Achieving scalability with custom locks

The talk was accepted to the conference program

Ivan Savu



The talk will cover following topics:

Memory architecture - CPU/Memory gap, memory hierarchy, multiprocessor cache, cache line contentions and its effects on scaling

Multiprocessor RW Lock - Fast reader/writer lock that scales linearly for read

0-bit spin lock - Lock that effectively uses no memory, allowing for cheap fine grained locking.